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\section{General purpose of the module}
\textit{Person in Charge: Guillem Cabo}

This module is the main interface between the SoC generated from Chisel and the DRAC core.
This top file gathers the signals with the name conventions of the SoC as the inputs/outputs of the module. That signals are connected to module instances, or reassigned to structures and connected to the instances of the \emph{datapath}, \emph{data cache interface} and \emph{instruction cache interface}.
